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[ Pobierz całość w formacie PDF ] University Program UP2 Education Kit ® December 2004, v3.1 User Guide Introduction The University Program UP2 Education Kit was designed to meet the needs of universities teaching digital logic design with state-of-the-art development tools and programmable logic devices (PLDs). The package provides all of the necessary tools for creating and implementing digital logic designs, including the following features: Quartus ® II Web-Edition development software ■ UP2 Education Board – ■ An EPF10K70 device in a 240-pin power quad flat pack (RQFP) package – An EPM7128S device in an 84-pin plastic J-lead chip carrier (PLCC) package ByteBlaster TM II parallel port download cable ■ Quartus II Software The Quartus II University software contains many of the features of the commercial version of the Quartus II software including a completely integrated design flow and an intuitive graphical user interface. This software supports schematic capture and text-based hardware description language (HDL) design entry, including Verilog HDL, VHDL, and the Altera ® Hardware Description Language (AHDL TM ). It also provides design programming, compilation, and verification support for all devices supported by the Quartus II Web-Edition software including the EPM7128S, and EPF10K70 devices. The Quartus II software can be freely distributed to students for installation on their personal computers and provides instant access to online help. 1 For information on how to install the Quartus II software on your computer, see “Software Installation” on page 17. UP2 Education Board The UP2 Education Board is a stand-alone experiment board based on a FLEX ® 10K device and includes a MAX ® 7000 device. When used with the Quartus II software, the board provides a superior platform for learning digital logic design using industry-standard development tools and PLDs. Altera Corporation 1 A-UG-UP1-3.1 P25-09231-01 University Program UP2 Education Kit User Guide The board is designed to meet the needs of instructors and students in a laboratory environment. The UP2 Education Board supports both look-up table (LUT) -based and product term-based architectures. The EPF10K70 device can be configured in-system with either the ByteBlaster II download cable or an EPC1 configuration device. Additional download cables can be purchased separately. The EPM7128S device can be programmed in-system with the ByteBlaster II download cable. EPF10K70 Device The EPF10K70 device is based on SRAM technology. It is available in a 240-pin RQFP package and has 3,744 logic elements (LEs) and nine embedded array blocks (EABs). Each LE consists of a four-input LUT, a programmable flipflop, and dedicated signal paths for carry-and-cascade functions. Each EAB provides 2,048 bits of memory which can be used to create RAM, ROM, or first-in first-out (FIFO) functions. EABs can also implement logic functions, such as multipliers, microcontrollers, state machines, and digital signal processing (DSP) functions. With 70,000 typical gates, the EPF10K70 device is ideal for intermediate to advanced digital design courses, including computer architecture, communications, and DSP applications. f For more information on FLEX 10K devices, see the FLEX 10K Embedded Programmable Logic Family Data Sheet . EPM7128S Device The EPM7128S device, a member of the high-density, high-performance MAX 7000S family, is based on erasable programmable read-only memory (EEPROM) elements. The EPM7128S device features a socket- mounted 84-pin plastic j-lead chip carrier (PLCC) package and has 128 macrocells. Each macrocell has a programmable- AND /fixed- OR array as well as a configurable register with independently-programmable clock, clock enable, clear, and preset functions. With a capacity of 2,500 gates and a simple architecture, the EPM7128S device is ideal for introductory designs as well as larger combinatorial and sequential logic functions. f For more information on MAX 7000 devices, go to the MAX 7000 Programmable Logic Device Family Data Sheet . ByteBlaster II Parallel Port Download Cable Designs can be easily and quickly downloaded into the UP2 Education Board using the ByteBlaster II download cable, which is a hardware interface to a standard parallel port. This cable sends programming or configuration data between the Quartus II software and the UP2 2 Altera Corporation University Program UP2 Education Kit User Guide Education Board. Because design changes are downloaded directly to the devices on the board, prototyping is easy and multiple design iterations can be accomplished in quick succession. UP2 Education Board Description The UP2 Education Board, shown in Figure 1, contains the features described in this section. Figure 1. UP2 Education Board Block Diagram FLEX_EXPAN_ R2 R1 VGA FLEX_DIGIT DC_IN C19 U5 CONF_D TCK POWER C2 TDI TDO RAW –+ –DC+ EPC1 P1 P2 EPF10K20 EPF10K70 or EPF10K70 MAX_DIGIT P7 D1 D9 D5 D6 D7 D8 D13 D14 D15 D16 D2 D3 D4 D10 D11 D12 FLEX_SWITCH EPM7128S P4 P3 P8 P5 P6 P9 P10 FLEX_EXPAN_ DC_IN & RAW Power Input The DC_IN power input accepts a 2.5-mm 5.55-mm female connector. The acceptable DC input is 7 to 9 V at a minimum of 350 mA. The RAW power input consists of two holes for connecting an unregulated power source. The hole marked with a plus sign (+) is the positive input; the hole marked with a minus sign (–) is board-common. × Oscillator The UP2 Education Board contains a 25.175-MHz crystal oscillator. The output of the oscillator drives a global clock input on the EPM7128S device (pin 83) and a global clock input on the FLEX 10K device (pin 91). Altera Corporation 3 University Program UP2 Education Kit User Guide JTAG_IN Header The 10-pin female plug on the ByteBlaster II download cable connects with the JTAG_IN 10-pin male header on the UP2 Education Board. The board provides power and ground to the ByteBlaster II download cable. Data is shifted into the devices via the TDI pin and shifted out of the devices via the TDO pin. Table 1 identifies the JTAG_IN pin names when the ByteBlaster II is operating in Joint Test Action Group (JTAG) mode. Table 1. JTAG_IN 10-Pin Header Pin-Outs Pin JTAG Signal 1 TCK 2 GND 3 TDO 4 VCC 5 TMS 6 No Connect 7 No Connect 8 No Connect 9 TDI 10 GND Jumpers The UP2 Education Board has four three-pin jumpers ( TDI , TDO , DEVICE , and BOARD ) that set the JTAG configuration. The JTAG chain can be set for a variety of configurations (i.e., to program only the EPM7128S device, to configure only the FLEX 10K device, to configure and program both devices, or to connect multiple UP2 Education Boards together). Figure 2 shows the positions of the three connectors (C1, C2, and C3) on each of the four jumpers. 4 Altera Corporation University Program UP2 Education Kit User Guide Figure 2. Position of C1, C2 & C3 Connectors TDI TDO DEVICE BOARD C1 C1 C1 C1 C2 C2 C2 C2 C3 C3 C3 C3 Table 2 defines the settings for each configuration. Table 2. JTAG Jumper Settings Desired Action TDI TDO DEVICE BOARD Program EPM7128S device only C1 & C2 C1 & C2 C1 & C2 C1 & C2 Configure FLEX 10K device only C2 & C3 C2 & C3 C1 & C2 C1 & C2 Program/configure both devices (1) C2 & C3 C1 & C2 C2 & C3 C1 & C2 Connect multiple boards together (2) C2 & C3 OPEN C2 & C3 C2 & C3 Notes to Table 2: (1) The first device in the JTAG chain is the FLEX 10K device, and the second device is the EPM7128S device. (2) The first device in the JTAG chain is the FLEX 10K device, and the second device is the EPM7128S device. The last board in the chain must be set for a single board configuration (i.e., for programming only the EPM7128S device, configuring only the FLEX 10K device, or configuring/programming both devices). The last board cannot be set for connecting multiple boards together. During configuration, the green CONF_D LED will turn off and the green TCK LED will modulate to indicate that data is transferring. After the device has successfully configured, the CONF_D LED will illuminate. f For information on how to program or configure the EPF10K70, or EPM7128S devices, see “Programming or Configuring Devices” on page 18. Altera Corporation 5
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